(1) Field of the Invention
The present invention relates to methods of fabricating and testing semiconductor chips, and more specifically to a novel pad design for a semiconductor chip or die allowing optimization of die testing to be accomplished.
(2) Description of Prior Art
The semiconductor industry is continually striving to increase performance of semiconductor chips while still reducing the fabrication or processing costs of these same chips. Reductions in fabrication costs have been accomplished via elimination of, or the combination of specific process steps or sequences such as the deposition of doped semiconductor layers rather than the more time consuming deposition of an intrinsic layer followed by a doping procedure. In addition the development of advanced semiconductor apparatus such as rapid thermal processing (RTP) tools have allowed the time needed for specific processes to be reduced. One aspect of processing, testing of the completed semiconductor chip, has not evidenced the cost optimization attention applied to other semiconductor processes.
This invention will describe a new pad organization for a semiconductor chip which will allow reduction of testing time for a specific chip to be realized. Prior art such as Whetsel in U.S. Pat. No. 6,326,801 B1, Littlebury in U.S. Pat. No. 5,012,187, Yasuda et al in U.S. Pat. No. 6,469,327 B1, Loughmiller et al in U.S. Pat. No. 6,396,300 B1, and Quinn et al in U.S. Pat. No. 4,685,998, disclose various contact pad designs, however none of the above prior art describe the novel pad design disclosed in this present invention in which specific chip pad designs for improving for improving testing and reducing costs are featured.